The present invention relates to a programmable sequence controller of the type that in addition to a logic operation processor, is provided also with an arithmetic operation processor for executing arithmetic operation commands included, though being unable to be executed by the logic operation processor, in a sequence control program.
With the requirements for complicated sequence control, there has recently become necessary a sequence controller wherein an arithmetic operation function for addition, substraction, comparison, etc. is given in addition to a logic operation function for testing the operational states (i.e. ON-OFF) of input elements such as limit switches, magnetic relays, etc. with the results of energizing or deenergizing a selected one of the output elements based upon the results of such tests.
For the purpose of meeting such requirement, an attempt may be made to use as operation processing means of sequence controllers a microcomputer which is capable of executing both logic and arithmetic operations. In this attempt, however, drawbacks may be raised in that the format of instruction words of the microcomputer and the architecture of the same are not necessarily suitable to the execution of sequence control programs and in that high speed execution of sequence control programs is impossible since each sequence control instruction cannot be executed without executions of several tens of microcomputer program instructions. Therefore, a scan cycle time taken to scan once all of stored sequence control instructions is rendered longer than the response time of conventional relay circuits, and this invites inconvenience in sequence control.
Further, there has heretofore been suggested a sequence controller which in addition to a high-speed logic operation processor of random logic type, is provided with an arithmetic operation processor composed of a microcomputer. In this controller, logic operation commands are executed by the high-speed logic operation processor, while arithmetic operation commands such as addition commands, subtraction commands, etc. which are unable to be executed by the logic operation processor are executed by the arithmetic operation processor, and it is thus possible to execute the arithmetic operations without substantially slowing the execution speed of the logic operations.
Where like this, a part of a sequence control is executed by the arithmetic operation processor, the logic operation processor must decode any read-out sequence instruction of the sequence control program so as to issue instructions regarding operations that the arithmetic operation processor is to execute, and the arithmetic operation processor must send out a completion signal to inform the logic operation processor that the arithmetic operation processor has completed its operation to execute. To this end, the prior sequence controller is provided with an information exchange memory accessible by both of the logic and arithmetic operation processors, and the operation instructions and the completion signal are exchanged between the processors by writing a logic value "1" into predetermined bits of a certain memory area of the information exchange memory and by reading out the signal statuses of the predetermined bits. It is therefore necessary for the prior art sequence controller to be also provided with, in addition to the information exchange memory, an access control circuit which periodically switches memory addresses of the information exchange memory for enabling the logic and arithmetic operation processors to alternately access the exchange memory.
Moreover, the prior art sequence controller involves the following problems due to the fact that the two operation processors cooperate in the above-described manner. First, the execution of sequence control must be halted to prevent the access by the logic operation processor to the information exchange memory while the access thereto is made by the arithmetic operation processor. This causes the scan cycle time that is taken to execute once all instructions of a sequence control program to be extended or prolonged so that unfavorable influences are exerted upon sequence control operation. Secondly, when a sequence instruction including an arithmetic operation command is read out from a sequence program memory, the logic operation processor only instructs through the information exchange memory the arithmetic operation processor to execute the arithmetic operation command, before reading out the next contiguous sequence instruction. Although the completion of operation by the arithmetic operation processor is immediately communicated to the logic operation processor through the exchange memory, the result of the arithmetic operation is not immediately reflected in the sequence control, but is reflected on that in a successive scan cycle. That is, in the prior art sequence controller, the delay of one scan cycle time is made until the result of any arithmetic operation is reflected on the flow of the controlled sequence, and this causes inconvenience in sequence control. Particularly, where there is required a sequence control in which a plurality of data are added for comparison with a preset value and in which the control flow is changed in dependence upon the results of such comparison, a sequence program therefor is programmed in such a way of confirming the completion of one arithmetic operation in advance of the execution of a successive arithmetic operation, and therefore, the delay of one scan cycle time is made each time one arithmetic operation is executed. For this reason, it may practically be impossible for the prior art sequence controller to execute a sequence program which includes a plurality of arithmetic operation commands each causing time delay in sequence control.